1. Field of the Invention
The present invention relates to semiconductor memory devices and more particularly, to semiconductor memory devices including a clock control circuit that generates clock signals to control the input and output operations of data input and output buffers of the semiconductor memory device and data input and output operations method thereof.
2. Discussion of Related Art
In general, the data input and output operations of a semiconductor memory device that is operated in synchronization with a clock signal, such as a synchronous semiconductor memory device, is performed in synchronization with internal clock signals.
In other words, in a write operation, a data input buffer of the synchronous semiconductor memory device outputs received external input data to an internal circuit in synchronization with an internal clock signal. Furthermore, in a read operation, a data output buffer of the synchronous semiconductor memory device outputs internal output data, which are received from the internal circuit, to an external apparatus in synchronization with the internal clock signal.
The data input and output operations of the semiconductor memory device will be described in more detail below with reference to FIGS. 1 and 2.
FIG. 1 is a schematic block diagram of a clock control circuit and data input and output buffers of a semiconductor memory device in the related art. FIG. 2 is a timing diagram of signals related to the operation of the clock control circuit and the data input and output buffers shown in FIG. 1.
Referring to FIG. 1, a clock buffer 11 receives an external clock signal (EXCLK) and outputs an input clock signal (CLK_DQ). A clock repeater 12 outputs an input control clock signal (CTDB_DIN) and an output control clock signal (CTDB_DOUT) based on the input clock signal (CLK_DQ). A data input buffer 13 receives external input data (DIN) and outputs internal input data (IDIN) to an internal circuit (not shown) in response to the input control clock signal (CTDB_DIN). A data output buffer 14 receives internal output data (IDOUT) from an internal circuit and outputs external output data (DOUT) to an external apparatus in response to the output control clock signal (CTDB_DOUT).
The input control clock signal (CTDB_DIN) and the output control clock signal (CTDB_OUT) have the same phase.
As shown in FIG. 2, the chip enable signal (/CE) is disabled and a write command (not shown) is input to the semiconductor memory device. Furthermore, when the address valid signal (/ADV) is disabled, the address signal (ADD) is input to the semiconductor memory device. Meanwhile, when the address valid signal (/ADV) is disabled, the write enable signal (/WE) is disabled. The clock repeater 12 consecutively outputs the input control clock signal (CTDB_DIN) and the output control clock signal (CTDB_OUT) whenever receiving the input clock signal (CLK_DQ) (i.e., whenever the input clock signal (CLK_DQ) is toggled). Therefore, the data input buffer 13 consecutively operates in response to the input control clock signals (CTDB_DIN) that are consecutively toggled in periods where external input data (DIN, ID0 to ID3) are not received.
The data output buffer 14 also consecutively operates in response to the output control clock signal (CTDB_OUT) in period where internal output data (IDOUT, OD0 to OD3) are not received. If the clock repeater 12, the data input buffer 13 and the data output buffer 14 are consecutively operated as described above, the amount of unnecessary current consumption is increased. This will be described in more detail below.
The clock repeater 12 includes a plurality of transistors (not shown). The transistors have a relatively high current driving ability. The reason why the transistors have a relatively high current driving ability is for supplying the input control clock signal (CTDB_DIN) and the output control clock signal (CTDB_OUT) to the data input buffer 13 and the data output buffer 14, which have a relatively high resistance component.
Since the transistors have a relatively high current driving ability as described above, a relatively great amount of current is consumed when the transistors are driven. Furthermore, whenever the input control clock signal (CTDB_DIN) and the output control clock signal (CTDB_OUT) are toggled, the data input buffer 13 and the data output buffer 14 are operated, consuming lots of current.
As described above, the clock repeater 12 of the related art consecutively toggles the input control clock signal (CTDB_DIN) and the output control clock signal (CTDB_OUT) regardless of an input or output time point of data. Therefore, a problem arises because the amount of unnecessary current consumption is increased.
This problem is more profound in the case where semiconductor memory devices including the clock repeater 12 are applied to mobile products. That is, the mobile products must operate for a long period of time at low power. To reduce power consumption, power consumption of semiconductor chips included in the mobile products must be reduced.
Power consumption of the semiconductor memory device is, however, increased due to the consecutive operation of the clock repeater 12. This makes it impossible for the mobile products to operate for a long period of time.